Precise oxide dissolution

ABSTRACT

In a Semiconductor-on-Insulator (SeOI) wafer that includes a thin working layer made from one or more semiconductor material(s); a support layer, and a buried oxide (BOX) layer between the working layer and the support layer, a method of decreasing the thickness of the BOX layer by dissolving it at a dissolution rate that is controlled and set to be below 0.06 Å/sec in order to avoid increasing Dit. The Dit after dissolution of the BOX layer is typically below 1E12 cm-2 eV-1.

The invention concerns a method for dissolving the buried oxide layer ofa SeOI (Semiconductor-On-Insulator) wafer in order to decrease thethickness of said buried oxide layer. The invention also concerns a SeOIwafer obtained after dissolving the buried oxide of a starting SeOIwafer by such a method.

A SeOI wafer is understood in this text as a wafer comprising:

-   -   a thin working layer made from one or more semiconductor        material(s), such as silicon,    -   a support layer, and    -   a buried oxide (BOX) layer between the working layer and the        support layer.

The invention is particularly well adapted for producing SeOI wafershaving a BOX which is an Ultra Thin Buried Oxide (UTBOX) layer. In thistext a UTBOX layer is understood as a buried BOX having a thicknesswhich is less than 500 Å.

SeOI wafers with an UTBOX layer are becoming a material of choice formodern advanced CMOS applications.

A promising method for manufacturing SeOI wafers with an UTBOX layerimplies dissolving the BOX of a starting SeOI wafer, in order to bringthe thickness of said BOX down to a desired value.

Some attempts for dissolving the BOX of a SeOI wafer have requestedannealing the starting wafer at over 1300° C. for several hours. Suchattempts were therefore not adapted to an industrial processing of thewafers.

WO2006/059586 discloses a method for completely dissolving the BOX of astarting SeOI wafer. In this method the SeOI wafer is annealed at atemperature which is preferably over 1100° C., in an atmosphere which ismade e.g. of Argon or hydrogen. The starting SeOI has a working Si layerwhich is thicker than 150 nm (1500 Å) in order to prevent the excessiveformation of a particular type of defects known as voids. This documenttherefore discloses potentially interesting information for enhancingthe quality of the wafers obtained.

However, quality issues remain to be solved concerning SeOI wafershaving a BOX which has been thinned by dissolution.

In particular, the Dit of the SeOI obtained is representative of theelectrical quality of the wafer obtained. The Dit is related to theinterface trap density. It characterizes the interface between theworking layer and the BOX layer.

It is an object of the invention to provide a quality SeOI, inparticular with an UTBOX layer, having a good (i.e. low) Dit. A low Ditcan in this text be understood as a Dit under 1E12 cm⁻² eV⁻¹.

It would also be desirable to obtain, if possible, the SeOI wafers witha yield compatible with usual industrial conditions.

It is another object of the invention to provide a method formanufacturing quality SeOI with an UTBOX layer and a low Dit.

Still another object of the invention is to provide a method which iscompatible with high volume SeOI wafer manufacturing.

To this end, the present invention provides a method and a SeOI waferaccording to the claims.

Other features, objects and advantages of the invention shall beunderstood in greater detail in reading the following description, whichis illustrated by the following figures:

FIG. 1 shows a model of BOX dissolution in Argon ambient, and especiallyoxygen distribution in SeOI wafer during anneal,

FIGS. 2 a and 2 b are, respectively, maps of the dissolved BOX thicknessand etched Si thickness over a SeOI wafer annealed at 1200° C. for 1hour,

FIG. 3 is a graph showing the evolution of the amount of etched top Siin a SeOI as a function of the thickness of dissolved BOX measured inthe same locations of the SeOI,

FIG. 4 is a graph showing the evolution of the thickness of dissolvedBOX in a SeOI as a function of the thickness of the top Si layer and theannealing time at 1200° C.,

FIG. 5 is a graph showing the evolution of the thickness of dissolvedBOX in a SeOI as a function of the thickness of the top Si layer and theannealing time at 1150° C.,

FIG. 6 is a cross sectional TEM image of an annealed SeOI wafer, showingin particular the amount of BOX dissolved after annealing,

FIG. 7 is a graph showing the evolution of the Dit associated to a SeOIhaving undergone annealing for dissolving its BOX, as a function of theBOX dissolution rate obtained during the annealing,

FIG. 8 is a table showing linear and parabolic coefficients used in amodel of BOX dissolution in Argon ambient,

FIG. 9 is a table gathering electrical parameters extracted fromPseudo-MOSFET measurements, associated with SeOI having dissolutionannealing under different conditions.

Annealing of SeOI wafer is carried out in an atmosphere which issubstantially oxygen-free, such as an atmosphere of pure Argon orhydrogen or their mixture, and preferably in pure Argon with Oxygencontent below 1 ppm.

In the case of a SeOI having a thin top layer (inferior to about 500 nm)(e.g. in Si), the BOX dissolution is determined by oxygen transportthrough the top layer and evaporation from the surface, rather thandiffusion into the base wafer. Using non oxidized ambient can increasedissolution rate.

With reference to FIG. 1, a model of BOX dissolution in Argon ambientand at high temperature is described hereafter.

There are several processes Pi, which define oxide dissolution rate insteady-state conditions:

P1. Diffusion of interstitial oxygen O_(i) from the base wafer, whichleads to growth of buried oxide at the BOX/base interface

P2. Decomposition of the BOX at the BOX/top Si interface into O_(i) andSi, which results in Si epitaxial regrowth at the top interface

P3. Diffusion of interstitial oxygen through the top Si layer

P4. Reaction of O_(i) with silicon at the top Si surface resulting involatile SiO

Si+O_(i)→SiO(g)   (1)

P5. Etching of the top Si layer by residual oxygen contamination in theannealing atmosphere, which competes with the reaction (1)

O₂+Si→SiO₂

SiO₂+2 Si→2 SiO(g)   (2)

P6. Gas phase SiO transport through Argon ambient.

More precisely, in steady-state conditions the oxide dissolution rate isdetermined by the slowest of the mechanisms of the oxygen transport fromthe oxide.

If oxygen is considered to be in equilibrium at the SiO₂/Si interfacesand if interstitial oxygen concentration at the interfaces is equal tooxygen solid solubility at the anneal temperature, process P1 can beneglected. Indeed, flux of oxygen atoms J₁ coming from the basesubstrate is decreasing with time t:

$\begin{matrix}{{J_{1} = {\left( {C_{sub} - C_{0}} \right)\sqrt{\frac{D}{\pi \; t}}}},} & (3)\end{matrix}$

while diffusion flux J₂ through the top Si layer is constant:

$\begin{matrix}{{J_{2} = \frac{D\left( {C_{0} - C^{*}} \right)}{\delta_{si}}},} & (4)\end{matrix}$

where C₀, D is interstitial oxygen solubility and diffusivity in silicon[14], δ_(si) is the thickness of top Si layer and C*, C_(sub) is theinterstitial oxygen concentration at the top Si surface and in the basewafer, respectively.

Estimations for the top Si thickness of approximately 0.1 μm show thatthe flux J₂ will be larger than J₁ already after 1 sec anneal at 1200°C. We can also assume that oxide decomposition/epitaxial Si regrowth isfast and is not a limiting factor of oxide dissolution kinetics. Thisassumption is supported by the literature data on oxygen precipitationkinetics, where it was found that oxygen precipitate dissolution isdiffusion limited rather than reaction limited process.

Chemical reaction (1) is the first order reaction if the effect ofresidual partial pressure of oxygen in Argon is neglected. So,proportional relation between concentration of interstitial oxygen atthe top surface C* and partial pressure of SiO in Argon at the topsurface P* can be written:

C*=K P*.   (5)

Transfer of SiO from Si surface through Argon can be described by mixedgas diffusion and forced convection. The mass transfer coefficient kwill depend on geometry of the system, gas parameters, temperature andthickness of boundary layer, which depends on local gas velocity:

J₃=kP*·  (6)

Finally, for each dissolved molecule of buried oxide one silicon atom isremoved from the top Si layer through evaporation of SiO. Thus, Si toplayer will be etched with the rate proportional to the BOX etching rate:

Δδ_(box)=(N_(si)/N_(sio2))Δδ_(si),   (7)

where N_(si)=5×10²² cm⁻³, and N_(sio2)=2.3×10²² cm⁻³. Taking intoaccount that Si atom flux can be expressed through top silicon layerthickness

$\begin{matrix}{J_{3} = {{- 2}N_{si}\frac{\delta_{si}}{t}}} & (8)\end{matrix}$

and combining equations (4)-(8) leads to differential equation for theSi layer thickness with the solution:

$\begin{matrix}{{{\frac{\delta_{si}^{2} - \delta_{0}^{2}}{2{Dt}} + \frac{\left( {\delta_{si} - \delta_{0}} \right)}{k^{*}t} + \frac{C_{0}}{2N_{si}}} = 0},} & (9)\end{matrix}$

where δ₀ is initial thickness of the top Si layer at t=0 and k* issimply equal to k/K. This equation can be rewritten in the form ofclassical linear-parabolic model:

$\begin{matrix}{{{\delta_{si}^{2} + {A\; \delta_{si}}} = {B\left( {\tau - t} \right)}}{with}} & (10) \\{{A = \frac{2D}{k^{*}}},\mspace{14mu} {B = \frac{D\; C_{0\;}}{N_{si}}},\mspace{14mu} {\tau = {\frac{\delta_{0}^{2} + {A\; \delta_{0}}}{B}.}}} & (11)\end{matrix}$

There could be two limiting cases for oxide dissolution. When masstransport through gas ambient is fast, dissolution is limited byinterstitial oxygen diffusion and the dissolution rate is inverselyproportional to the top Si layer thickness. In the other case of gastransport limited regime, the dissolution rate depends only ontemperature and local mass transport coefficient k*. According to thismodel, the dissolution rate of the BOX does neither depend on the BOXthickness nor on the base wafer material.

FIG. 2 to 9 show results from different experiments carried out toassess SeOI wafers processed under different conditions.

300 mm commercially available SOI wafers produced by Smart Cut™technique were used. Buried oxide was prepared by thermal oxidation ofthe donor Si wafers in atmosphere of oxygen with H₂O, resulting in thebonding interface at the BOX/base wafer interface. Interstitial oxygenconcentration in the base wafers was 1.2×10¹⁸ cm⁻³ as determined by FTIRspectroscopy with a calibration constant of 4.8×10¹⁷ cm⁻². Wafers wereannealed in Argon atmosphere in vertical furnaces, specially designed toreduce residual oxygen gas contamination. Four different types offurnaces were tested with the equivalent results. Concentration ofoxygen gas in the exhaust was below 5 ppm during anneal. Annealing wasperformed at 1100° C.-1200° C. for a time from a few minutes to a fewhours. For all the experiments, the same slow temperature ramps wereused to minimize slip generation at high temperatures. Thickness of topSi and BOX layers varied in the range of 500-5000 Å and 150-1500 Å,respectively.

FIG. 2 shows maps of thickness difference before and after 1 hourannealing at 1200° C. for BOX (a) and top Si (b) layers. Thickness ofthe layers before the annealing was 1450 Å and 500 Å, respectively.

Thickness of the layers before and after the dissolution was measured bya spectroscopic ellipsometer. 49 data points with 5 mm edge exclusionwere taken for each wafer. A three-layer model with standard dispersionfunctions for Si and SiO₂ was used and showed a very good fit of thespectra. Few samples were analyzed by XTEM and XRR (X-ray reflection) toconfirm ellipsometry data. Thickness of the layers determined by thesetechniques agreed well within the accuracy of the techniques.

It is clearly seen that the dissolution of buried oxide occurs at 1200°C., when interstitial oxygen in the substrate is supersaturated. Thepatterns of dissolved BOX and top silicon layer correlate very well witheach other and with the distribution of gas flow in the verticalfurnace. Dissolution rate of oxide and etching rate of Si are higherwhere gas velocity is higher indicating that the process occurs in themixed diffusion/gas transport regime.

FIG. 3 shows proportionality between dissolved BOX thickness and etchedtop Si layer thickness. Each point represents thickness measurements fordifferent wafers annealed at 1200° C. for different times, averaged atthe positions with the constant radius. The data fit very well to thestraight line with the slope of 45%, which is the ratio of specificvolumes of Si and SiO₂, as predicted by Eq. 7. This points out that noadditional Si etching takes place due to the reaction (2) at 1200° C.,indicating high quality of annealing ambient.

A temperature above 1150° C. is therefore suitable for BOX dissolution,and preferably a temperature of 1200° C.

Experimental dependence of dissolved BOX thickness on the initialthickness of the top Si layer is shown in the FIGS. 4 and 5 for 1200° C.and 1150° C. annealing, respectively. Solid lines are theoretical fit ofthe Eq. 10 and Eq. 7 for the edge points and dashed lines for the centerpoints.

It appears that dissolution characteristics are better in the case ofanneal temperature of 1200° C. than that of 1150° C. An also anneal timein the case of temperature condition above 1150° C. is more compatiblewith high volume manufacturing of SOI wafers, and preferably atemperature of 1200° C.

For each annealing condition the same value of B, but different A wereused to fit edge and center data. B and A are coefficients as shown inEq. 10. To account for the BOX dissolution during long temperature ramp,the data for each annealing time and temperature were fit with separateeffective coefficients Aeff and Beff, but center and edge points for thesame annealing conditions were fit with the same value of Beff.

As all the anneals had the same ramp profiles, it is possible to extractisothermal values of the coefficients B and A by plotting the dependenceof Beff (and Beff/Aeff, respectively) on holding time at the temperatureof the anneal as shown in the insert of FIG. 4. The slope of the curvewill give the value of B (more precisely, this linearity is valid in thecase of small etched Si thickness only). Results of the fitting of theparameters together with the theoretical values of B are presented inFIG. 8.

At 1200° C. dissolution of the BOX at the wafer edge is limited by theinterstitial oxygen diffusion in the top Si layer with excellentagreement between experimental and theoretical B value calculated fromEq. 11.

As expected, at the wafer center, gas transport slows down dissolution,resulting in higher A values (A center values of 30 Å and 1070 Å vs. Aedge values of 0 Å and 236 Å, respectively at 1200° C. and 1150° C.).With a temperature decrease, dissolution rate kinetics slow down andsignificantly deviate from diffusion-limited regime, but still show agas velocity pattern.

Also, initial Si thickness appears to have an influence on dissolutionrate. The thinner the initial Si thickness is, the faster thedissolution rate.

FIG. 6 presents TEM image of top Si/BOX interface of SOI wafer annealedin Argon at 1200° C. for 1 hr. Roughness of the Si/SiO₂ interface is 2-3atomic planes, which is comparable with the roughness of SOI interfacesbefore the anneal (and typical for thermal oxides). No crystallographicdefect has been found in the top Si layer or at the boundary of regrownSi layer.

Pseudo-MOSFET technique is very sensitive to interface quality of thetop SeOI interface. Therefore electrical characterization of the top Silayer and top interface was carried out by a Pseudo-MOSFET technique.

This technique uses the particular structure of SeOI wafers to produceMOSFET-like current transport characteristics. A bias ramp is applied onthe substrate, which acts as a transistor gate.

The buried oxide serves as gate oxide and two metallic probes applied onthe film act as source and drain. Because the source and drain are notdoped, the device can be operated as an n-MOS as well as a p-MOStransistor. The typical parameters, hole and electron mobility (μh andμe), subthreshold swing (S), interface trap density (D_(IT)), flat-bandand threshold voltages (V_(FB) and V_(T)) can be extracted in a similarway to fully processed MOSFETs. For all measurements, the source isgrounded, the drain is biased at a low value (200 mV) to insure linearmode operation and the gate voltage (V_(G)) is swept from 0V towardsaccumulation (inversion) to extract majority (minority) carriercharacteristics (respectively).. Set of samples annealed in differentconditions was measured by Pseudo-MOSFET method to assess the electricalquality of the interface and of the regrown Si. Values of hole andelectron mobility were extracted from the curve

$\frac{I_{D}}{\sqrt{Gm}}{{vs}V}_{G}$

where Gm is the transconductance

$\frac{\partial I_{D}}{\partial V_{G}},$

as described in. S is taken as the inverse of the subthreshold slope ofthe Log(I_(D)) vs V_(G) curve. Interface trap density is calculated fromS using the equation:

$\begin{matrix}{{D_{IT} = {\frac{C_{OX}}{q}\left\lbrack {\frac{S}{\frac{kT}{q}{\log (10)}} - \left( {1 + \frac{C_{Si}}{C_{OX}}} \right)} \right\rbrack}},} & (12)\end{matrix}$

where q is the elementary charge, kT/q is the thermal potential, C_(si)and C_(ox) are the film and buried oxide capacitance respectively. FIG.9 summarizes the results of Pseudo-MOSFET measurements.

Because the top surface of the Si film is not passivated during themeasurement, the extracted parameters depend on the top Si filmthickness. Therefore, for a valid comparison, results are given also forthe equivalent wafers, which have not undergone BOX dissolutiontreatment. The thinnest sample annealed did not reveal transistorbehaviour, indicating that the highest dissolution rate resulted in badquality of the interface.

Results of Dit dependence on the BOX dissolution rate are plotted on theFIG. 7. In FIG. 7, square symbols refer to the measurements of sampleswith different Si layer thickness and diamonds symbols refer to themeasurements of control samples with the same Si layer thickness, butwithout annealing.

Control samples results abscissa are virtual since the examples did notundergo any annealing; therefore no BOX dissolution rates are available.They were plotted to ease comparison with samples that underwentannealing.

From FIG. 7 and FIG. 9, it is clearly seen that interface trap densityincreases and carrier mobility decreases with increasing BOX dissolutionrate, while annealing time or amount of the dissolved BOX seem to havelittle or no effect. We could speculate that the high rate of solidphase Si regrowth can result in defects at Si/SiO₂ interface, but forthe BOX dissolution rate below 0.06 Å/sec electrical quality of annealedSOI structures is comparable with the reference wafers with Dit valuesbelow 1E12 cm⁻²e⁻¹. The lower the Dit value is, the better the electricquality of the wafer is.

Therefore, according to an aspect of the invention the dissolution rateis controlled to be kept at a limited value, under 0.06 angstroms/sec.

This aspect of the invention goes against the natural tendency one couldhave to maximize the dissolution rate in order to speed up the process.

In order to keep the dissolution rate compatible with industrialapplications, the maximum value mentioned above should be respected butthe dissolution rate should be kept not too low. As an example, adissolution rate below 0.01Å/sec is not compatible with high volumemanufacturing. The dissolution rate should therefore preferably be keptabove this value.

Significant reduction of buried oxide thickness without degradation ofthe wafer quality can be achieved by annealing of the SeOI wafers inoxygen free ambient. Oxide dissolution rate is determined byinterstitial oxygen diffusion through the top Si layer and inverselydepends on top Si thickness.

Generally speaking, the applicant has determined that the control of thedissolution rate was obtained in the first place by controlling thefollowing parameters:

-   -   the control of the atmosphere under which dissolution is carried        out, and/or    -   the control of the temperature under which dissolution is        carried out, and/or    -   the choice of the thickness of said working layer.

When anneal is carried out in non oxidized ambient such as Argon withless than 1 ppm oxygen (or more generally an atmosphere with less than 1ppm oxygen), high rate oxide dissolution is possible and can becontrolled by temperature and initial top Si thickness.

More precisely, optimal oxide dissolution rate in Argon ambient iscontrolled by setting anneal temperature above 1150° C. and selectinginitial top Si thickness between 550 and 2300 Å.

1-8. (canceled)
 9. In a Semiconductor-on-Insulator (SeOI) wafer thatincludes a thin working layer made from one or more semiconductormaterial(s); a support layer, and a buried oxide (BOX) layer between theworking layer and the support layer, the improvement which comprisesdecreasing the thickness of the BOX layer by dissolving it at adissolution rate that is controlled and set to be below 0.06 Å/sec inorder to avoid increasing Dit.
 10. The invention of claim 9, wherein thedissolution rate is further set to be above about 0.01 Å/sec.
 11. Theinvention of claim 9, wherein dissolution rate is controlled bycontrolling the atmosphere under which dissolution is carried out. 12.The invention of claim 11, wherein the atmosphere is controlled so as tocontain less than 1 ppm oxygen.
 13. The invention of claim 9, whereindissolution rate is controlled by controlling the temperature underwhich dissolution is carried out.
 14. The invention of claim 11, whereinthe temperature is controlled so as to be above 1150° C.
 15. Theinvention of claim 9, wherein dissolution rate is controlled byselecting the thickness of the working layer.
 16. The invention of claim15, wherein the thickness of the working layer is selected so as to bebetween 550 and 2300 Å.
 17. The invention of claim 9, wherein the Ditafter dissolution of the BOX layer is below 1E12 cm-2 eV-1.
 18. ASemiconductor-on-Insulator (SeOI) wafer comprising a thin working layermade from one or more semiconductor material(s); a support layer; and aburied oxide (BOX) layer of reduced thickness between the working layerand the support layer, with the SeOI wafer having a Dit below 1E12 cm-2eV-1.
 19. The SeOI wafer of claim 18, wherein the reduced thickness ofthe BOX layer is below 200 Å.